When fabricating a DRAM on a p-type substrate, there are frequently formed the n-channel MOS transistors of the memory cell regions and the n- and p-channel MOS transistors of the peripheral circuit regions in other well tubs. This has the following advantages: first, the memory cell regions are not affected by the noises induced in the peripheral circuit regions; second, the substrate bias of the memory cell regions may be controlled independently of the peripheral circuit region; third, the short-channel effect of the peripheral circuit region may be readily controlled; fourth, the substrate voltage generator circuit may be made more small.
However, it is required that the p-well of the memory cell region should be separated from the p-type silicon substrate in order to form the n-channel MOS transistors of the memory cell regions and the n- and p-channel MOS transistors of the peripheral circuit regions in the other wells, so that there must needs be formed the n-wells deeper than the p-wells of the memory cell regions, and thus to cover them. This results in the triple well structure, as disclosed in U.S. Pat. No. 5,397,734 entitled "Method of Fabricating a Semiconductor Memory Device Having a Triple Well Structure".
FIG. 1 illustrates the general structure of a DRAM made of hierarchical word lines or sub-word lines. This includes a plurality of memory cell regions 10, a plurality of sub-word line decoders (SWDs) 21 respectively arranged in the regions 20 between adjacent memory cell regions 10 in the word line direction, and a plurality of sense amplifiers (SAs) 32 respectively arranged in the regions 30 between the memory cell regions 10 in the direction of the bit lines (not shown), through which a memory cell is selected to sense its data by means of SA. The drive circuits (DRVs) for supplying a voltage source and decoding signals Pxj to the above regions 20 and 30 are arranged in the DRV regions 40 between the SWD regions 20 and SA regions 30. One of them is the first drive circuit 41 to drive the decoding signals PXID and PXIB of different levels VPP and VINT to corresponding SWD 21, and the other the second drive circuit 42 to supply a source voltage to the P- and N-latch sense amplifiers 33 and 34 as shown in FIG. 2A.
FIG. 2A is a circuit diagram for illustrating a drive circuit of the P-latch SA conventionally used in DRAM, and FIG. 2B a drive circuit of a conventional SWD used n DRAM. FIG. 3A is a plane view for illustrating the structure of the twin well, and FIG. 3B a cross sectional view taken along line 3-3' in FIG. 3A. As shown in the drawings, DRAM using the p-type semiconductor substrate 1 comprises NMOS transistors in the p-type substrate 1 and PMOS transistors in the n-well in the SA region 30, where ground voltage VSS is applied as the well bias voltage of the transistors constituting the N-latch SA 34 of the SA 32, and the internal voltage VINT as the well bias voltage of the PMOS transistors. In this case, the SA region 30 may be laid out by means of the twin well structure, as shown in FIGS. 3A and 3B.
Referring to FIG. 1, the drive circuits 41 and 42 of SWD and SA are arranged together in the DRV region 40, where at least two wells are required because the decoding signal Pxj is driven by two voltage sources, for example, VPP and VINT due to the inverter circuits IV1, IV2 and IV3 constituting the SWD drive circuit 41. Namely, the PMOS transistors of the inverter circuits IV1, IV2 and IV3 are separately arranged both in the n-well biased by the voltage VPP and in the n-well biased by the voltage VINT. Additionally required are at least two n-wells for the PMOS transistors applied with a different well-bias source voltage. In this respect, it is substantially impossible to arrange the drive circuits 41 and 42 in the region 40 defined by the SWD region 20 and SA region 30, as shown in FIG. 1. Namely, after determining the space W between the wells and the space S between the boundary of the element active region and the boundary of the well, it is impossible to form the PMOS transistors in the remaining DRV region A(=L-2*[S+W+S'+W'], where L is the width of SWD, as shown in FIG. 6A). In order to cope with this problem, it has been proposed to reduce the size of the SWD and SA drive elements arranged in the DRV region 40 or to arrange them in the external region except the cell region 10. However, this proposition degrades the capacity of the drive elements or lowers the operational speed due to the delay time inhering in the signal lines connecting the external drive circuit with the internal SA or SWD. Or otherwise, the DRV region 40 may be increased to resolve such problem, but this results in increase of the chip size.